// +FHDR============================================================================/
// Author       : hjie
// Creat Time   : 2025/03/06 12:06:24
// File Name    : ddr4_mdl.sv
// Module Ver   : Vx.x
//
//
// All Rights Reserved
//
// ---------------------------------------------------------------------------------/
//
// Modification History:
// V1.0         initial
//
// -FHDR============================================================================/
// 
// ddr4_mdl
//    |---
// 
`timescale 1ns/1ps

`include "arch_defines.v"
`include "StateTable.svp"
module ddr4_mdl 
(
    input                        [16:0] ddr4_addr                   , 
    input                         [1:0] ddr4_ba                     , 
    input                               ddr4_bg                     , 
    input                               ddr4_cke                    , 
    input                               ddr4_ck_p                   , 
    input                               ddr4_ck_n                   , 
    input                               ddr4_reset_n                , 
    input                               ddr4_cs_n                   , 
    inout                        [15:0] ddr4_dq                     , 
    inout                         [1:0] ddr4_dqs_p                  , 
    inout                         [1:0] ddr4_dqs_n                  , 
    inout                         [1:0] ddr4_dm_dbi_n               , 
    input                               ddr4_odt                    , 
    input                               ddr4_act_n                  , 
    input                               ddr4_ten                    , 
    input                               ddr4_par                      
);
import arch_package::*;
import proj_package::*;

genvar                                  i                           ;
bit                                     en_model                    ;
 
//StateTable _state();
//UTYPE_dutconfig _dut_config;
//DDR4_cmd active_cmd = new();
//UTYPE_TimingParameters timing;
//UTYPE_cmdtype driving_cmd;
parameter UTYPE_density CONFIGURED_DENSITY = _4G;
parameter int CONFIGURED_DQ_BITS = 16;
parameter int CONFIGURED_RANKS = 1;

initial begin
    #200
    en_model = 1'b0; 
    #5 en_model = 1'b1;
end

tri model_enable = en_model;

DDR4_if #
(
    .CONFIGURED_DQ_BITS             (16                         )  
) 
iDDR4
();

ddr4_model #
(
    .CONFIGURED_DQ_BITS             (CONFIGURED_DQ_BITS         ), 
    .CONFIGURED_DENSITY             (CONFIGURED_DENSITY         ), 
    .CONFIGURED_RANKS               (CONFIGURED_RANKS           )  
) 
u0_ddr4_model
(
    .model_enable                   (model_enable               ), 
    .iDDR4                          (iDDR4                      )  
);

assign iDDR4.CK = {ddr4_ck_p,ddr4_ck_n};
assign iDDR4.ACT_n     =  ddr4_act_n;
assign iDDR4.RAS_n_A16 =  ddr4_addr[16];
assign iDDR4.CAS_n_A15 =  ddr4_addr[15];
assign iDDR4.WE_n_A14  =  ddr4_addr[14];
//assign iDDR4.ALERT_n   =  'd1;
assign iDDR4.PARITY    =  ddr4_par;
assign iDDR4.RESET_n   =  ddr4_reset_n;
assign iDDR4.TEN       =  ddr4_ten;
assign iDDR4.CS_n      =  ddr4_cs_n;
assign iDDR4.CKE       =  ddr4_cke;
assign iDDR4.ODT       =  ddr4_odt;
assign iDDR4.BG        =  ddr4_bg;
assign iDDR4.BA        =  ddr4_ba;
assign iDDR4.ADDR      =  ddr4_addr[13:0];
assign iDDR4.ADDR_17   =  'd0;
assign iDDR4.ZQ        =  'd1;
assign iDDR4.PWR       =  'd1;
assign iDDR4.VREF_CA   =  'd1;
assign iDDR4.VREF_DQ   =  'd1;



generate
for(i=0;i<2;i=i+1)begin:ddr_dqsm_loop

tran dm (iDDR4.DM_n[i],ddr4_dm_dbi_n[i]);
tran dqs_t(iDDR4.DQS_t[i],ddr4_dqs_p[i]);
tran dqs_c(iDDR4.DQS_c[i],ddr4_dqs_n[i]);
end

for(i=0;i<16;i=i+1)begin:ddr_dq_loop
tran dq(iDDR4.DQ[i],ddr4_dq[i]);
end
endgenerate

endmodule




